Algorithm to improve packet processing performance using existing caching schemes
US7406567B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2002 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Nov 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for improving the speed of packet switching in a routing platform that maps shared I/O memory into two address spaces. The first address space is mapped with the cache attribute and uses the cache write through attribute. Addresses in this address space are not equal to the physical address in the shared I/O memory and are translated to the physical addresses. Code executed by the CPU to switch packets utilizes the first address space to access packet data. The second address space is mapped with the non-cache attribute and addresses in this space are equal to the physical addresses in the shared I/O memory. The second address space is utilized by I/O devices when accessing shared I/O memory. Addresses of buffers for storing packet data in the shared I/O memory are converted from the first address space to the second address space when given to I/O devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.