Selectively changeable line width memory
US7406579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2005 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Aug 16, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides for selectively changing a line width for a memory, i.e., selecting one of a plurality of line widths for a memory. The selected line width is used in communicating with one or more processors. This provides increased flexibility and efficiency for communicating with the memory. In particular, a register can be set based on a desired line width, and subsequently used when locating data in the memory. The selected line width can be associated with each data block in the memory to allow multiple line widths to be used simultaneously. When implemented in a cache, multiple ways of the cache can be processed as a group to provide data during a single memory operation. The line width can be varied based on a task, a processor, and/or a performance evaluation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.