Method, system, and apparatus for efficient evaluation of boolean expressions
US7406592B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 2004 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Mar 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/427
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and computer-readable media are provided for efficiently evaluation Boolean expressions. According to the method, the Boolean expression is expressed using pre-fix notation. Each element in the pre-fix expression is then parsed. For each first operand for a Boolean operation, the value of the operand is determined. This may include evaluating a GUID. When an operator and a second operand are encountered, a decision is made as to whether the second operand should be evaluated. The determination as to whether the second operand should be evaluated is made based upon the value of the first operand and the type of operator. If the second operand need not be evaluated, no evaluation is performed thereby saving time and memory space. The evaluation of the Boolean expression continues in this manner until the entire expression has been evaluated. If the Boolean expression is evaluated as true, the program module associated with the Boolean expression may be loaded. Otherwise, the program module will not be loaded.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.