Simulated error injection system in target device for testing host system
US7406628B2 · kind B2 · utility
9Cited by
42References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2004 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Jul 3, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and device are provided that use a sequencer in the device to control interactions on an interface bus. The sequencer is programmed to interrupt a co-processor before execution of a command. Based on the interrupt signal and a stored error mode page, a false error condition is initiated by further programming the sequencer to operate abnormally. After recovery from the error condition, the sequencer is reprogrammed to operate normally.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.