Error reporting network in multiprocessor computer
US7406632B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2003 |
| Grant date | Jul 29, 2008 |
| Priority date | — |
| Expiry date | Jul 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0772
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high-performance, high-reliable backplane bus has a simple configuration and operation. An error reporting network (ERN) provides an inexpensive approach to collecting the error state of a whole system in a uniform and consistent way. The uniformity allows for simpler interface software and for standardized hardware handling of classes of errors. In a preferred embodiment, serial error registers are used, minimizing implementation cost and making the software interface to the serial registers much easier. Serial error information is transferred over a separate data path from the main parallel bus, decreasing the chance of the original error corrupting the error information. Each CPU is provided with a local copy of the entire body of error information. The redundancy minimizes the impact of a possible CPU failure and allows the CPUs to coordinate error recovery.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.