Patent · US Active

DMOS device with sealed channel processing

US7407851B2 · kind B2 · utility

2Cited by

7References

30Claims

0Family size

Inventors

Gayle W. Miller · Colorado Springs, US
Irwin Rathbun · Colorado Springs, US
Stefan Schwantes · Heilbronn, DE
Michael Graf · Leutenbach, DE
Volker Dudek · Ditzingen, DE

Key dates

Filing date	Mar 22, 2006
Grant date	Aug 5, 2008
Priority date	—
Expiry date	Jan 31, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH10D64/516
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.