Semiconductor pixel arrays with reduced sensitivity to defects
US7408195B2 · kind B2 · utility
2Cited by
29References
21Claims
0Family size
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Key dates
| Filing date | Sep 4, 2003 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Sep 4, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/802
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel structure is described, comprising at least two selection switches coupled in series to improve the yield of the pixel. Also an array comprising such pixel structures logically organized in rows and columns is described, as well as a method for selecting a row or column of pixel structures in such an array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.