Vertical transistor structure for use in semiconductor device and method of forming the same
US7408224B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2005 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Aug 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/027
Abstract
According to some embodiments, a structure of vertical transistor includes gate electrodes distanced by a predetermined interval in an active region, formed in a vertical shape to have a predetermined depth from a top surface of a semiconductor substrate. A gate insulation layer is formed between one side wall of the gate electrode and the substrate. A gate spacer is formed in another sidewall of the gate electrode, covering the gate electrode. A contact plug is formed between the gate spacer. A plug impurity layer is formed in a lower part of the contact plug, and source and drain are formed opposite to the gate electrode within the active region. Thereby, an area occupied by a gate electrode is substantially reduced, so a unit memory cell has a 4F2 structure, reducing a memory cell size, by forming a vertical-type gate electrode within an active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.