Method for hardware sorted fragment composition
US7408549B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2004 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Jan 12, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/503
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics system including a frame buffer and a processing unit. The frame buffer contains N slots per pixel. Slots are used to store fragments. Suppose the N slots for a given pixel are occupied. In response to having received (or generated) a new fragment for the pixel, the processing unit may (a) blend the two backmost slots to liberate space for the new fragment, (b) blend the new fragment with the backmost slot in a first order, or, (c) blend the new fragment and the backmost slot in a second order. The choice of (a), (b) or (c) depends on the relationship of the new fragment's z value to the z values of the two backmost slots. The processing unit may be programmably configured to perform multi-pass order independent transparency in either front-to-back order or back-to-front order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.