System packet interface
US7408878B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2003 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Nov 30, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/30
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An apparatus including a first integrated circuit (IC), a second IC, and an interface coupling the first IC to the second IC. The interface transfers payload control information between the first IC and the second IC utilizing a number of data transmission lines. On the clock cycle transition following the transfer of payload control information, the interface transfers packetized data between the first IC and the second IC at a data rate of at least approximately 20 Gbps utilizing the same transmission lines. A one-bit control signal is used by the interface to identify when payload control information is present on all of the data transmission lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.