Data sampling method and apparatus with alternating edge sampling phase detection for loop characteristic stabilization
US7409031B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2003 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Aug 26, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for 2× oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter environments and can be implemented with small hardware overhead. A transceiver that embodies the invention can be implemented as a CMOS integrated circuit using a 0.18 μm CMOS process, with the transceiver chip being capable of recovering data having a data rate of up to 11.5 Gbps from a signal received over a serial link, while consuming no more than 540 mW from 1.8V supply, and with a bit error rate of less than 10−12.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.