Timing error reduction in QKD systems
US7409162B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 20, 2004 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | May 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/34
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems and methods for reducing or eliminating timing errors in a quantum key distribution (QKD) system (100) are disclosed. The QKD system has a pulse generator with retimer (PGRT) that includes a field-programmable gate array (FPGA) (or FPGA output) which is used as a timing generator (TG). While an FPGA has the desired degree of programmability for use in a QKD system, it also suffers from undue amounts of jitter in the digital output. The present invention utilizes emitter-coupled logic (ECL) to reduce the timing jitter from the FPGA by coupling two ECL delays (ECL delay 1 and ECL delay 2) to the FPGA and to retiming block, and by using an ECL logical AND gate to set the pulse width of the various synchronization signals. An embodiment of the present invention includes multiple clock domains having individual clocks (CLK), phase-lock loops (PLLs), retiming circuits (RT) and timing generators (TG) for robust jitter reduction and hence highly accurate QKD system timing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.