Linearly scalable finite impulse response filter
US7409418B2 · kind B2 · utility
3Cited by
10References
10Claims
0Family size
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Key dates
| Filing date | Nov 17, 2003 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Feb 5, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2017/0298
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved Finite Impulse Response (FIR) filter is presented which provides linear scalability and implementation without the need for delay lines. A multiprocessor architecture includes a plurality of ALUs (Arithmetic and Logic Unit), Multipliers units, Data cache, and Load/Store units sharing a common Instruction cache. A multi-port memory is also included. An assigning functionality assigns to each available processing unit the computation of specified unique partial product terms and the accumulation of each computed partial product on specified output sample values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.