Integrated circuit having reduced pin count
US7409484B2 · kind B2 · utility
1Cited by
5References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 28, 2005 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Feb 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method according to one embodiment may include decoupling a CAUDIO/SPKR#/BVD2 signal line from a PC Card controller integrated circuit. The method of this embodiment may also include controlling, by the PC Card controller integrated circuit, at least one PC Card independently of the CAUDIO/SPKR#/BVD2 signal line. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.