Method and apparatus for compressing VLIW instruction and sharing subinstructions
US7409530B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2004 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Nov 2, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A VLIW instruction format is introduced having a set of control bits which identify subinstruction sharing conditions. At compilation the VLIW instruction is analyzed to identify subinstruction sharing opportunities. Such opportunities are encoded in the control bits of the instruction. Before the instruction is moved into the instruction cache, the instruction is compressed into the new format to delete select redundant occurrences of a subinstruction. Specifically, where a subinstruction is to be shared by corresponding functional processing units of respective clusters, the subinstruction need only appear in the instruction once. The redundant appearance is deleted. The control bits are decoded at instruction parsing time to route a shared subinstruction to the associated functional processing units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.