Method and apparatus for reducing number of cycles required to checkpoint instructions in a multi-threaded processor
US7409589B2 · kind B2 · utility
12Cited by
47References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 27, 2005 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Nov 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1407
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for reducing the number of cycles required to checkpoint instructions in a multi-threaded microprocessor that has dispatch group checkpointing. A determination is made in a first stage of a checkpoint pipeline whether checkpointing can occur for a group of instructions. The results of processing the group of instructions flow to a second stage of the checkpoint pipeline regardless of whether the group of instructions is ready to checkpoint. If the group of instructions is ready to checkpoint, the group of instructions is checkpointed in a third stage of the checkpoint pipeline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.