Pseudo-random wait-state and pseudo-random latency components
US7409608B1 · kind B1 · utility
3Cited by
7References
29Claims
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Key dates
| Filing date | Apr 20, 2004 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Nov 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/267
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for testing logic, particularly arbitration logic on a programmable chip. Secondary components on a programmable chip are configured with delay mechanisms operable to pseudo-randomly delay responses to requests received using arbitration logic. Requests are typically generated by primary components. The delay mechanisms can be used to test the ability of a programmable chip system to handle a variety of secondary component wait-state and latency characteristics. The delay mechanism can also be used to improve system performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.