System and method for reverse error correction coding
US7409622B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2005 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Dec 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for Reverse Error Correction Coding. The system includes a Constraint encoder, an Error Correction Code encoder, and a uniform interleaver. The Constraint encoder receives a source data stream and generates a first intermediate encoded data stream satisfying a first predetermined timing data constraint. The Error Correction Code encoder receives the first intermediate encoded data stream and generates a second intermediate encoded data stream having one or more Error Correction Code based elements. The uniform interleaver receives the second intermediate encoded data stream and generates a channel data stream having the one or more Error Correction Code based elements and satisfying a second predetermined timing data constraint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.