Techniques for modeling a circuit board structure
US7409667B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2005 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Sep 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09736
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A technique generates circuit board modeling data for a circuit board structure having multiple layers. The technique includes receiving a set of global circuit board dimension parameters from a user. The set of global circuit board dimension parameters defines a set of global circuit board dimensions of the circuit board structure. The technique further includes forming, for each layer, a set of individual circuit board dimension parameters defining a set of individual circuit board dimensions for that layer based on the set of global circuit board dimension parameters. The technique further includes providing a script for use by a 3D modeling subsystem. The script includes a set of circuit board design values based on the set of individual circuit board dimension parameters formed for each layer. Other properties such as layer width and thickness, via dimensions, etc. are handled in a similar manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.