Scheduling logic on a programmable device implemented using a high-level language
US7409670B1 · kind B1 · utility
25Cited by
34References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2004 |
| Grant date | Aug 5, 2008 |
| Priority date | — |
| Expiry date | Jan 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A portion of a program written in a high-level language is automatically selected for hardware acceleration. Dedicated ports are generated to allow the hardware accelerator to handle pointer referencing and dereferencing. A hardware accelerator is generated to perform pipelined processing of instructions. The number of stages implemented for pipelined processing is at least partially dependent on the latency associated with accessing secondary components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.