Method of manufacturing and structure of polycrystalline semiconductor thin-film heterostructures on dissimilar substrates
US7410882B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2004 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Feb 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to various exemplary embodiments of this invention, a method of producing a semiconductor structure is provided that includes providing a layered structure on a first substrate, the layered structure including a silicon layer that is provided over a first dielectric layer, a first dielectric layer that is provided over an etch-stop layer, the etch-stop layer provided over a buffer layer, the buffer layer provided over a sacrificial layer, and a sacrificial layer provided over a first substrate. Moreover, various exemplary embodiments of the methods of this invention provide for a second substrate over the layered structure, separating the first substrate and the sacrificial layer from the buffer layer, separating the buffer layer and the etch-stop layer from the first dielectric layer and providing a drain electrode and a source electrode over the layered structure. Moreover, according to various exemplary embodiments of the devices of this invention, a transistor device is provided that includes a substrate, a gate electrode over the substrate, a laser recrystallized polycrystalline semiconductor layer over the gate electrode and a source electrode and a drain electrode …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.