Driver/equalizer with compensation for equalization non-idealities
US7411422B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2005 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Oct 12, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03343
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high speed serial data communication system includes provisions for the correction of equalization errors, particularly those errors introduced by equalizer non-idealities. The equalization is achieved at the data transmitter, and is based on dynamic current subtraction at the output of a differential pair. When bit time>0, the error current is removed or subtracted from the total driver current, thereby maintaining a constant total current from bit time 0 to bit time>0. The same result can also be achieved by subtracting current when bit time>0 using field effect transistors of the opposite gender. The error current can be determined empirically from simulation or through feedback using a replica of the driver. The circuits for achieving equalization error correction and the resulting electrical network analysis are shown and described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.