Frequency and/or phase lock loops with beat frequency estimation
US7411461B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2004 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Jun 1, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A control loop (10) for producing an output signal with a stable nominal frequency is provided. The control loop includes inputs for reference (11) and oscillator (25) output signals, a beat frequency generator (12) for producing a signal with a frequency that is the difference between the oscillator and reference signal frequencies, an ADC (14) to convert the beat frequency to a digital beat frequency signal, an estimator (17) for estimating the frequency or phase of the beat signal, an adder (18) for combining an offset and modulation signal and the estimated frequency or phase of the beat signal into an added signal, and a DAC (23) for generating an analogue control signal for controlling the oscillator output frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.