Apparatus and method for switchable conditional execution in a VLIW processor
US7412591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2005 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Jul 31, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/38585
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoder loads and decodes instructions from a fetch unit for decoding and sending the decoded instructions to the ALU with control units for execution. The register file stores and forwards the results on result buses to the decoders. The execution of a VLIW instruction includes a fetch stage, a decode stage, plural execution stages and a write-back stage. The invention has the features of approximate ASIC timing by conditional write-back with the compiler support for the conditional write-back, condition resolved just before write-back, software selective conditional issue and conditional write-back modes, and without hardware interlock/dependence checking for the VLIW processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.