Method and apparatus for optimizing distributed multiplexed bus interconnects
US7412670B2 · kind B2 · utility
1Cited by
34References
19Claims
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Key dates
| Filing date | Apr 1, 2005 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Nov 30, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses for optimizing distributed multiplexed bus interconnects are described. Parameters of components that make up a distributed multiplexed bus interconnect may be optimized, such as an amount of area on a chip occupied by the component, an amount of power consumed by the component, etc., while satisfying existing timing constraints between nodes of a distributed multiplexed bus interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.