Method and computer program for management of synchronous and asynchronous clock domain crossing in integrated circuit design
US7412678B2 · kind B2 · utility
7Cited by
15References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 2, 2004 |
| Grant date | Aug 12, 2008 |
| Priority date | — |
| Expiry date | Aug 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and computer program are disclosed for managing synchronous and asynchronous clock domain crossings that include steps of: (a) receiving as input an integrated circuit design; (b) identifying paths between synchronous clock domains and paths between asynchronous clock domains in the integrated circuit design; and (c) if a path between synchronous clock domains is defined as a false path in the integrated circuit design, then reporting a fatal violation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.