Stacked capacitor and method for producing stacked capacitors for dynamic memory cells
US7413951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 2006 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Oct 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
A method produces stacked capacitors for dynamic memory cells, in which a number of trenches (48) are formed in the masking layer (40), each trench (48) being arranged above a respective contact plug (26) and extending from the top (42) of the masking layer (40) to the contact plugs (26). A conductive layer (50) covers the side walls (49) of the trenches (48) and the contact plugs (26) in order to form a first electrode (60) of a stacked capacitor (12). In an upper region (63), which is remote from the contact stack (26), the conductive layer (50) is replaced by an insulating layer, so that it is not possible for a short circuit to arise in the event of any adhesion between adjacent electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.