Multi-step process for forming a barrier film for use in copper layer formation
US7413984B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2007 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Apr 10, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate with a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum is formed on the first barrier layer. A copper seed layer is formed on the second barrier layer and implanted with barrier ions and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.