Architecture for implementing an integrated capacitance
US7414459B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 2006 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Jul 29, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An architecture for implementing an integrated capacity includes a capacitive block inserted between first and second voltage reference. The block is formed The block is formed from elementary capacitive modules. An enable block is inserted between the first voltage reference and the capacitive block and includes switches connected to the elementary capacitive modules and driven on their control terminals by control signals. Each switch of the enable block is inserted between the first voltage reference and a first end of a corresponding elementary capacitive module. A verify and enable circuit is connected to the first voltage reference, as well as at the input of the first end of the elementary capacitive modules and at the output of the control terminals of the switches of the enable block. The verify and enable circuit detects the presence of a current value in each of the elementary capacitive modules and, if said current is detected, disables that elementary capacitive module of the capacitive block using the corresponding switch of the enable block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.