Dynamic bias circuit
US7414559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 13, 2007 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Apr 13, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/662
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that is one of a plurality of register frames forming a data chain. The plurality of register frames are serially linked and data within the data chain is shifted among the plurality of register frames. Through a time domain multiplexing scheme, the D2A can be shared by control knobs of the equalization circuit. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data within the data chain is shifting according to the clock period. A method for adjusting a signal through a bias circuit is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.