Semiconductor memory device
US7414874B2 · kind B2 · utility
1Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2006 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Oct 27, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor memory device comprising a memory cell array block, and a circuit region arranged with the memory cell array block along a first direction. The circuit region comprises a first region and a second region arranged with the first region along the first direction. The first region is provided with a first circuit and a second circuit which are aligned in a second direction perpendicular to the first direction. The second region is provided with a plurality of third circuits which are aligned in the second direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.