Circuit synchronization over asynchronous links
US7415002B2 · kind B2 · utility
1Cited by
21References
54Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2003 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Jun 15, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0697
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A device that synchronizes circuits over asynchronous links is disclosed. Some embodiments of the invention include a device that comprises a plurality of circuits. One of the plurality of circuits is designated as a “master” circuit. The master circuit is configured to send a first synchronization signal to one or more of the plurality of circuits, and each circuit that receives the first synchronization signal is configured to responsively send a second synchronization signal to one or more of the plurality of circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.