Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory
US7415595B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2005 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | May 25, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable network that may be configured to selectively provide connectivity between the memory units, the accelerator units, and the processor core. Each of the accelerator units may be configured to perform one or more dedicated functions. The processor core may include an execution unit that may be configured to execute instructions that are associated with datapath flow control. The programmable network may be configured to selectively provide the connectivity in response to execution of particular instructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.