Self-repairing of microprocessor array structures
US7415644B2 · kind B2 · utility
15Cited by
4References
4Claims
0Family size
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Key dates
| Filing date | Oct 22, 2004 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Aug 21, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A level of indirection is utilized when writing to a microprocessor array structure, thereby masking hard faults in the array structure. Among other benefits, this minimizes the use of a backward error recovery mechanism with its inherent delay for recovery. The indirection is used to effectively remove from use faulty portions of the array structure and substitute spare, functioning portions to perform the duties of the faulty portions. Thus, for example, faulty rows in microprocessor array structures are mapped out in favor of substitute, functioning rows.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.