Error correction code generator
US7415660B2 · kind B2 · utility
1Cited by
2References
37Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 6, 2004 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | May 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2909
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An error correction code generator uses an additional static random access memory (SRAM) or a multi-symbol encoder to improve the encoding efficiency. During the encoding operation, the number of the data access of the dynamic random access memory (DRAM) with the row address switching can be reduced considerably via using the additional SRAM or multi-symbol encoder. Hence, the efficiency of the data access of the DRAM is improved and the encoding time of the error correction code generator is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.