Optimal mapping of LUT based FPGA
US7415681B2 · kind B2 · utility
7Cited by
1References
25Claims
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Key dates
| Filing date | Dec 29, 2004 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Jan 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for improved optimal mapping of LUT based FPGA's. The invention comprises performing a topological sort on the network to be mapped, whereby the network is represented in form of a Directed Acyclic Graph. The system locates feasible reconvergent paths existing from transitive fan-ins of each node using a Reconvergent Path Locator for replicating fan-outs of the nodes in the DAG, and therefore optimizing the number of LUT's and the time consumed in the mapping process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.