Method and apparatus for a chaotic computing module
US7415683B2 · kind B2 · utility
4Cited by
9References
20Claims
0Family size
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Key dates
| Filing date | Dec 15, 2005 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Jul 28, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N7/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.