Method and computer program for incremental placement and routing with nested shells
US7415687B2 · kind B2 · utility
5Cited by
0References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 5, 2005 |
| Grant date | Aug 19, 2008 |
| Priority date | — |
| Expiry date | Nov 15, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of placing and routing an integrated circuit design includes generating an initial placement and routing for at least a portion of an integrated circuit design. The initial placement and routing of the integrated circuit design is analyzed to find a critical location and is partitioned into a series of nested shells. Each shell surrounds the critical location and each preceding shell. An ordering of the shells and at least one of a timing constraint and an area constraint are selected for each shell. Each shell is placed and routed in the order selected according to the timing constraint and area constraint.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.