Neo-wafer device and method
US7417323B2 · kind B2 · utility
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5References
5Claims
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Assignee
Inventor
Key dates
| Filing date | Nov 6, 2003 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Nov 6, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A neo-wafer made from integrated circuit die and methods for making a neo-wafer are disclosed. A substrate is provided and includes a dielectric layer with conductive pads for the receiving of one or more integrated circuit die. Die are flip-chip bonded to the conductive pads and all voids under-filled. The neo-wafer is thinned to expose the conductive pads, creating a neo-wafer from which stackable neo-layers with known good die can be singulated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.