External power ring with multiple tapings to reduce IR drop in integrated circuit
US7417328B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2001 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Mar 6, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A power bus for use in an IC is disclosed that is configured as a grid and further formed using strips formed on I/O pads such as data I/O and multi-level voltage I/O pads. An IC is disclosed comprising a power supply I/O pad and a data I/O pad which are made of a deposited conductor. The power supply I/O pad is connected to a power bus and the data I/O pad is connected to circuitry. A strip of deposited conductor is formed closely adjacent to the data I/O pad wherein the strip is connected to the power bus. Parallel paths are developed within the integrated circuit to distribute power within the circuit. A similar approach is taken with respect to multi-level I/O pads. The power bus provide for reduced IR drops and better power supplies to core logic within an integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.