Direct digital interpolative synthesis
US7417510B2 · kind B2 · utility
64Cited by
1References
23Claims
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Key dates
| Filing date | Oct 17, 2006 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Dec 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock synthesis circuit includes a delta sigma modulator that receives a divide ratio and generates an integer portion and a digital quantization error (a fractional portion). A fractional-N divider divides a received signal according to a divide control value corresponding to the integer portion and generates a divided signal. A phase interpolator adjusts a phase of the divided signal according to the digital quantization error to thereby reduce noise associated with the fractional-N divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.