Systems and methods for resolving memory address collisions
US7417907B1 · kind B1 · utility
10Cited by
16References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 23, 2004 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Dec 23, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware implemented method for resolving collisions of memory addresses of a memory array is provided. In this hardware implemented method, a read memory address is compared with a write memory address. If the read and write memory addresses match, write data is directed from a data input to a data output, whereby the data input is further configured to input the write data to the memory array. A system and a memory chip for resolving collisions of memory addresses of a memory array are also described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.