Semiconductor memory device having hierarchically structured data lines and precharging means
US7417911B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2006 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Dec 25, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided comprising precharge circuits corresponding to global data line pairs, but not a precharge circuit corresponding to a local data line pair. In a command waiting state, data line selection switches are controlled to be in a connected state, so that the local data line pair and the global data line pairs are precharged all together while being connected to each other. In a command executing state, one of the data line selection switches, the one being not required for command execution, is in an open state. Similarly, a semiconductor memory device comprising only a precharge circuit corresponding to a local data line pair can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.