Egress selection switch architecture with power management
US7417985B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2004 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Mar 28, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/40
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus for reducing power consumption and digital logic noise in a time division multiplexed memory switch. The method is embodied in an egress selection switch (ESS) block architecture. The ESS block includes a data disable block which prevents the propagation of data, in particular ingress grains, to a given group of egress ports if the data is not selected by any of the egress ports in a given group. While the ingress data disable method partitions ports into groups and saves power by disabling the fanout tree from the root on a port group basis, the egress data disable method saves power on a port group basis by disabling the fanout tree from the tail end in addition to applying the ingress data disable method. The ESS block also includes an grain select block for selecting and storing a given ingress grain for eventual output to an egress port.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.