Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction
US7418574B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2003 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Mar 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06Q40/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline accelerator generates pipeline data from the host data. Alternatively, the pipeline accelerator generates the pipeline data, and the host processor generates the host data from the pipeline data. Because the peer-vector machine includes both a processor and a pipeline accelerator, it can often process data more efficiently than a machine that includes only processors or only accelerators. For example, one can design the peer-vector machine so that the host processor performs decision-making and non-mathematically intensive operations and the accelerator performs non-decision-making and mathematically intensive operations. By shifting the mathematically intensive operations to the accelerator, the peer-vector machine often can, for a given clock frequency, process data at a speed that surpasses the speed at which a processor-only machine can process the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.