Component with a dynamically reconfigurable architecture
US7418579B2 · kind B2 · utility
52Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2004 |
| Grant date | Aug 26, 2008 |
| Priority date | — |
| Expiry date | Sep 30, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a component with a large grain dynamically reconfigurable architecture for processing of data by processing units organized in rows and connected to each other through interconnections so as to enable processing in pipeline or parallel mode or in dependent rows mode. All data types may be processed and the component may process several applications at the same time. The choice of the grain, control at several levels with limited control interconnection resources and the data distribution circuit enable local or general reconfiguration of the component in one clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.