Semiconductor device fabrication method
US7419914B2 · kind B2 · utility
0Cited by
4References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 21, 2006 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Mar 23, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76814
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device with a borderless via/wiring structure includes the steps of performing borderless via etching using a resist mask to form a contact hole in an interlevel dielectric layer over a semiconductor substrate so as to expose two different metal materials of lower layer patterns in the contact hole; andperforming plasma irradiation using an H2O-containing gas prior to a wet process when removing the resist mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.