LDMOS device with improved ESD performance
US7420252B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2006 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Sep 18, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A semiconductor device includes a first doped region disposed on a first well in a semiconductor substrate; a second doped region disposed on a second well adjacent to the first well in the semiconductor substrate, the second doped region having a dopant density higher than that of the second well; and a gate structure overlying parts of the first and second wells for controlling a current flowing between the first and second doped regions. A first spacing distance from an interface between the second doped region and the second well to its closest edge of the gate structure is greater than 200 percent of a second spacing distance from a center point of second doped region to the edge of the gate structure, thereby increasing impedance against an electrostatic discharge (ESD) current flowing between the first and second doped regions during an ESD event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.