Solid state imager arrangements
US7420605B2 · kind B2 · utility
20Cited by
4References
48Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2003 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | Nov 6, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/80
Abstract
A solid state imager arrangement includes an image area, an output register which receives signal charge from the image area, a separate multiplication register into which signal charge from the output register is transferred, means for obtaining signal charge multiplication by transferring the charge through a sufficiently high field in elements of the multiplication register, and an additional register into which excess signal charge is transferred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.