Fault signature system for power management integrated circuits
US7420791B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2004 |
| Grant date | Sep 2, 2008 |
| Priority date | — |
| Expiry date | May 19, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31721
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A power management IC including a dual purpose pin, a fault detection system, and a fault signature system. The dual purpose pin performs a power management function during normal operation (e.g., a soft start pin coupled to an external capacitor, a set pin coupled to an external resistor, a frequency set pin coupled to a resistor-capacitor combination, etc.). The fault detection system senses any of multiple fault conditions and provides a corresponding fault indicator signal, each indicating a corresponding fault condition. The fault signature system generates a selected fault signature signal on the dual purpose pin, where each fault signature signal has a characteristic indicative of a corresponding fault condition. Thus, an existing pin on the IC is re-used to indicate the fault condition. The fault signature signal may be a unique voltage level, a unique charging rate, a unique frequency signal, or any a combination thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.